About: Giorgio Di Natale

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An Entity of Type : foaf:Person, within Data Space : data.idref.fr associated with source document(s)

Attributes	Values
type	Person
sameAs	Di Natale, Giorgio (19..-....) Di Natale, Giorgio (19..-....) Di Natale, Giorgio (19..-....)
Life Event	http://www.idref.fr/165791144/birth
preferred label	Di Natale, Giorgio (19..-....)
name	Giorgio Di Natale
dbpedia-owl:citizenship	http://sws.geonames.org/3175395/
Language	http://lexvo.org/id/iso639-3/ita
Given name	Giorgio
familyName	Di Natale
has biographical i...tion (Deprecated)	Chargé de recherches au CNRS, Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier (LIRMM) (en 2012). Directeur de recherche, TIMA - CNRS, Grenoble (2020)
gender	male
ORCID iD	0000-0001-8063-5388
Scopus ID	6603786965
is sameAs of	Di Natale, Giorgio (19..-....) Di Natale, Giorgio (19..-....)
is Thesis advisor of	http://www.sudoc.fr/168801302/id http://www.sudoc.fr/227416120/id http://www.sudoc.fr/268431094/id http://www.sudoc.fr/253991889/id http://www.sudoc.fr/268972109/id http://www.sudoc.fr/271982411/id http://www.sudoc.fr/276810899/id http://www.sudoc.fr/282395024/id
is Praeses of	http://www.sudoc.fr/257903097/id http://www.sudoc.fr/258445033/id http://www.sudoc.fr/271497998/id http://www.sudoc.fr/254954243/id http://www.sudoc.fr/25619159X/id http://www.sudoc.fr/257670688/id http://www.sudoc.fr/263053261/id http://www.sudoc.fr/258268743/id http://www.sudoc.fr/258979399/id http://www.sudoc.fr/25280144X/id http://www.sudoc.fr/250014378/id http://www.sudoc.fr/268852146/id http://www.sudoc.fr/266960073/id http://www.sudoc.fr/280201265/id
is Author of	Reliability of computing systems: From flip flops to variables Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memories Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies A Reliable Architecture for the Advanced Encryption Standard Chapter 9: Fault Detection in Crypto-devices A New Bulk Built-in Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies True random number generator based on nanomagnets TRUDEVICE: A COST Action on "Trustworthy Manufacturing and Utilization of Secure Devices" (Editorial) A New Scan Attack on RSA in Presence of Industrial Countermeasures Using Outliers to Detect Stealthy Hardware Trojan Triggering? Cross-layer system reliability assessment framework for hardware faults Sécurité des moyens de test des SoC Towards a Dependable True Random Number Generator With Self-Repair Capabilities High-Entropy STT-MTJ-based TRNG SECCS: SECure Context Saving for IoT Devices Evaluation of Concurrent Error Detection Techniques on the Advanced Encryption Standard Evaluation of Concurrent Error Detection Techniques on the Advanced Encryption Standard Rapport Technique de fin d'année, Contrat TOETS CT 302, Programme CEE CATRENE Is Side-Channel Analysis really reliable for detecting Hardware Trojans? Secure JTAG Implementation Using Schnorr Protocol TSVs Pre-Bond Testing: a test scheme for capturing BIST responses Introduction to Special Issue on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE) Laser-Induced Fault Simulation Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption Scan chain encryption in Test Standards Laser attacks on integrated circuits: from CMOS to FD-SOI Sensitivity to Laser Fault Injection: CMOS FD-SOI vs. CMOS bulk Rebooting Computing: The Challenges for Test and Reliability A Bulk Built-in Sensor for Detection of Fault Attacks Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN) An On-Line Fault Detection Scheme for SBoxes in Secure Circuits Low Cost Self-Test of Crypto-Devices Calibrating Bulk Built-in Current Sensors for Detecting Transient Faults Protection against Hardware Trojans with Logic Testing: Proposed Solutions and Challenges Ahead A new secure stream cipher for scan chain encryption Hardware Trojan Prevention using Layout-Level Design Approach MRAM-based PUF Digital-to-Analog Hardware Trojan Attacks PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection Validation Of Single BBICS Architecture In Detecting Multiple Faults TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-2009 - Rapport Technique de Fin d'année New Security Threats Against Chips Containing Scan Chain Structures Identification of Hardware Trojans triggering signals A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware Trojans Frontside Versus Backside Laser Injection: A Comparative Study 2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures Cross-Layer Early Reliability Evaluation for the Computing cOntinuum Faster-than-at-speed execution of functional programs: An experimental analysis New Testing Procedure for Finding Insertion Sites of Stealthy Hardware Trojans STT MRAM-Based PUFs Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS Do we need a holistic approach for the design of secure IoT systems? March Test BDN, a new March Test for Dynamic Faults Power Consumption Traces Realignment to Improve Differential Power Analysis tLIFTING : A Multi-level Delay-annotated Fault Simulator for Digital Circuits On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview A smart test controller for scan chains in secure circuits Hacking the Control Flow error detection mechanism Stream cipher-based scan encryption in test standards

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