About: Michel Renovell

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An Entity of Type : foaf:Person, within Data Space : data.idref.fr associated with source document(s)

Attributes	Values
type	Person
sameAs	Renovell, Michel (1956-....) Renovell, Michel (1956-....) Renovell, Michel (1956-....) Renovell, Michel (1956-....) Renovell, Michel (1956-....)
Life Event	http://www.idref.fr/031539130/birth
bnf-onto:FRBNF	12273494(xsd:integer)
preferred label	Renovell, Michel (1956-....)
name	Michel Renovell
dbpedia-owl:citizenship	http://sws.geonames.org/3017382/
Language	http://lexvo.org/id/iso639-3/fra
isni:identifierValid	0000000374226013
Given name	Michel
familyName	Renovell
note	Docteur en composants, signaux et systèmes (Montpellier 2, 1986). Directeur de recherche, Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier (2016)
gender	male
ORCID iD	0000-0002-3896-8231
Scopus ID	7006963596
is sameAs of	Renovell, Michel (1956-....) Renovell, Michel (1956-....)
is Thesis advisor of	http://www.sudoc.fr/188331115/id Modélisation de défauts paramétriques en vue de tests statiques et dynamiques http://www.sudoc.fr/144731428/id http://www.sudoc.fr/071505776/id http://www.sudoc.fr/047980060/id http://www.sudoc.fr/111402956/id http://www.sudoc.fr/131482866/id http://www.sudoc.fr/178611492/id Test des circuits configurables de type FPGA à base de SRAM http://www.sudoc.fr/128264187/id http://www.sudoc.fr/079495818/id http://www.sudoc.fr/246928549/id Test et testabilité des FPGA hiérarchiques à base de cellules mémoires SRAM http://www.sudoc.fr/246681209/id http://www.sudoc.fr/246750081/id http://www.sudoc.fr/247175382/id Analyse de l'impact du bruit de commutation sur les blocs digitaux des circuits intégrés CMOS http://www.sudoc.fr/247086215/id http://www.sudoc.fr/232694117/id Etude et modélisation électrique du court-circuit grille-canal dans le transistor MOS http://www.sudoc.fr/247060984/id Analogue Network of Converters, a DfT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SoC Test orienté utilisateur des circuits configurables de type FGPA à base de SRAM
is Praeses of	http://www.sudoc.fr/176515348/id http://www.sudoc.fr/176928006/id http://www.sudoc.fr/185408532/id http://www.sudoc.fr/257657401/id http://www.sudoc.fr/235022403/id
is Author of	http://www.sudoc.fr/005222907/id Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies System-in-Package, a Combination of Challenges and Solutions Low Voltage Testing of Gate Oxide Short in CMOS Technology Delay Testing of MOS Transistor with Gate Oxide Short An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects Implementing model redundancy in predictive alternate test to improve test confidence A Comparative Analysis of Indirect Measurement Selection Strategies for Analog/RF Alternate Testing New implementions of predictive alternate analog/RF test with augmented model redundancy Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies Rapport Technique de fin de Contrat NanoTEST 2A702, Programme CEE MEDEA+ Testing the Unidimensionnal Interconnect Architecture of Symmetrical SRAM-based FPGA Evaluation of ADC Static Parameters via Frequency Domain Simulating Resistive Bridging and Stuck-At Faults High Quality TPG for Delay Faults in Look-Up Tables of FPGAs On the Efficiency of Measuring ADC Dynamic Parameters to Detect ADC Static Errors Impact of Gate Oxide Reduction Failure on Analog Applications: Example of the Current Mirror A Compact Model for Electrical Simulation of MOS Transistor with Gate Oxide Short Defect Analysis of short defects in FinFET based logic cells Contrat NanoTEST 2A702 - Programme CEE MEDEA+ Delay Testing Viability of Gate Oxide Short Defect Contrat NanoTEST 2A702 - Programme CEE MEDEA - Rapport Technique de fin d'année The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002) Viability of a Delay Testing of Gate Oxide Short Transistors On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing Rapport Technique de fin d'année, Contrat TOETS CT 302, Programme CEE CATRENE Smart selection of indirect parameters for DC-based alternate RF IC testing Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies Behavior and test of open-gate defects in FinFET based cells Testing Global Interconnects of Field Programmable Analog Arrays Current testing in dynamic CMOS circuits Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs Test de Circuits et de Systèmes Intégrés “Analogue Network of Converters”: A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC ANC-Based Method for Testing Converters with Random-Phase Harmonics Conditions pour le Test de Pannes de Délai des Look-Up Table dans les FPGA à Base de SRAM Improving Defect Detection in Static-Voltage Testing Built-In Self-Test of Global Interconnects of Field Programmable Analog Arrays Fast and Fully-Efficient Test Flow for ADCs SIP Test Architectures Analysis of the Specification Influence on the Efficiency of an Optimized Test Flow for ADCs Models for Bridging Defects TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-2009 - Rapport Technique de Fin d'année Automatic Test Pattern Generation for Resistive Bridging Faults Mesure des Paramètres Statiques des Convertisseurs A/N par une Analyse Spectrale Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies First International Conference on Embedded Systems and Critical Applications (ICESCA 2008) Mitigating Read & Write Errors in STT-MRAM Memories under DVS Defect Analysis for Delay-Fault BIST in FPGAs

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